Riiven Threads
Solid State Drive
The Lie That Works
Save a file and watch the progress bar finish instantly. Nothing moved, nothing spun, and the data landed on a chip that is, at that very moment, failing. Every NAND flash cell wears out a little with each write, and the raw error rate on modern chips is high enough that the drive would be untrustworthy if it reported what it actually saw. Manufacturers ship these chips anyway. They sell you storage built on cells too leaky and too worn to trust on their own, and they charge a premium for it. So the question is not how solid state storage got fast. It is how anyone made a dying, error-prone chip safe enough to hold your only copy.
- 40errors/1kB
- Bit errors LDPC can correct per kilobyte in scaled flash.
- 10years
- Retention a well-built tunnel oxide holds with the power off.
- 100,000erase cycles
- Micron rating for an SLC block before it wears out.
- 28.5Gb/mmยฒ
- Areal density lost without precise lithographic overlay in 3D NAND.
How each idea was handed down
Solid State Drive inherited its parts in sequence. Each field handed its result to the next.
The inheritance, in order
- 1978 Quantum Tunneling and Floating-Gate Physicshanded down ↓
- 1987 Photolithographic Semiconductor Fabrication Engineeringhanded down ↓
- 2011 Flash Translation Layer and Wear-Leveling Algorithmshanded down ↓
- 2013 Error-Correcting Codes for NAND Reliability
Follow the inheritance, link by link.
Ordered from the earliest ancestor to the most recent heir.
Keystone
The math that made bad chips safe
A drive reads a page of scaled flash and dozens of bits come back wrong. It ships you the file corrected anyway.
Read a single page of modern flash and dozens of bits come back wrong, like a paragraph with random letters swapped. The drive has to fix them before you ever see the file. Early drives leaned on BCH codes, a scheme that catches a fixed number of errors, but below 20 nm the chips flipped more bits than BCH could repair. In 2013 Jiadong Wang and Jack Keil Wolf showed how LDPC codes, which weigh how confident each bit reading is instead of guessing yes or no, could rescue far dirtier pages. Their scheme corrects up to 40 bit errors per 1kB, enough to trust three-bit TLC cells that BCH alone could never make commercial. That correction is what turned cheap, dense, error-prone flash into storage.
Without this link
Without modern error-correcting codes such as BCH and LDPC, the high raw error rates of scaled MLC and TLC NAND would push application-level error rates past acceptable limits, so drives would silently corrupt data after modest wear. Below 20 nm, BCH-only schemes already fall short, forcing vendors toward much lower-density flash and conservative write limits that would collapse mainstream SSD capacity and lifetime.
Without BCH and LDPC codes correcting up to 40 bit errors per 1kB, flash becomes unreadable after a few thousand write cycles.
How we know
The 2013 JSAC work exploited multiple reads at slightly shifted reference voltages to build soft information, feeding LDPC decoders probabilities rather than hard binary decisions, which is what let them push correction past the BCH ceiling at 2x nm nodes.
Source: JSAC 2013 LDPC Flash (2013) · tier1
But correction only matters if the cell can hold a charge in the first place, and holding charge is a trick of physics.
Electrons that walk through a wall
A flash cell traps electrons behind an insulating wall so thin that electrons can slip straight through it.
A flash cell stores a bit as a puddle of electrons trapped behind a layer of insulation, held there whether the power is on or off. The trick is getting electrons across that wall on command. Fowler-Nordheim tunneling, electrons slipping through a barrier too thin to fully stop them, lets a voltage push charge in or pull it out. Eli Harari engineered oxides thin enough to tunnel through yet thick enough to leak slowly. Properly built 6-8 nm tunnel oxides keep the trapped charge for the 10 years of retention consumers expect. Without it, an SSD would forget everything the moment you unplugged it.
Without this link
Without quantum tunneling through thin oxides, floating-gate cells could not inject or remove electrons efficiently, so their threshold voltage would never shift in a controlled, digital way and bits could not be reliably stored. NAND arrays would lose non-volatile charge storage, forcing systems back to bulky mechanical or purely volatile memory with far lower density and no power-off retention.
Without Fowler-Nordheim tunneling in 6-8 nm oxides, flash cells miss the 10 years of retention and behave like volatile memory.
How we know
The physics traces to Fowler and Nordheim's 1928 description of field emission through a thin barrier; Harari's contribution was applying it to a manufacturable EEPROM cell in the late 1970s.
Source: IEEE Milestone Floating Gate EEPROM 1976-1978 (1978) · tier2
A cell that holds charge still wears out with every write, so something has to spread the damage evenly.
The traffic cop that spreads the wear
Save the same file a thousand times and, left alone, the drive would pound the same cells to death.
Every NAND block survives only so many erases before it dies, and real workloads hammer the same spots. Left alone, a few blocks would wear out while the rest sat fresh. The flash translation layer sits between your computer and the chip, remapping each write to a different physical block, like rotating tires so no tread wears first. Garbage collection tracks which blocks are tired and moves data off them. Micron rates SLC blocks for over 100000 erase cycles, but without wear-leveling a concentrated workload kills a few blocks long before that.
Without this link
Without the flash translation layer, the SSD cannot remap logical writes away from the same physical blocks, so hot data concentrates wear on a small subset of cells. Without wear-leveling and garbage collection, those blocks reach erase limits far sooner, while stale pages pile up and shrink the free space available for future writes.
Without wear-leveling, a few NAND blocks absorb most writes and fail long before their rated 100000 erase cycles.
How we know
The FTL also handles the mismatch between small logical writes and NAND's large erase blocks, so stale pages accumulate until garbage collection reclaims them, a process that itself consumes endurance and drives write amplification.
Source: Micron NFTL guide (2011) · tier2
Spreading wear buys endurance, but capacity comes from cramming billions of cells onto a single die.
Printing a billion pillars in tolerance
Stack 176 layers of memory on one chip and every layer has to line up within a few atoms.
A modern 3D NAND die stacks over 176 wordlines and more than a billion vertical memory pillars, aligned like floors in a skyscraper that cannot lean. Photolithography, printing circuit patterns with light, holds that alignment. Lose that precision and a die forfeits 28.5 Gb/mm2 of density, dropping terabyte drives back to gigabyte scale.
Without this link
Without photolithographic fabrication engineering, manufacturers could not stack and align over 176 vertical wordlines and more than a billion pillars on a single 3D NAND die, so terabyte-class drives would collapse back to megabyte or gigabyte scale. Precise patterning and overlay control keep the tiny channels, spacing, and multi-bit cells within tolerance; without them, density, yield, and endurance drop below usable levels.
Without precise photolithographic overlay, 3D NAND forfeits 28.5 Gb/mm2 of density, preventing 1Tb QLC dies from reaching practical capacity.
How we know
Source: Recent Progress on 3D NAND Flash Technologies (2021) · tier2
Watch
A visual companion to the fields above.
Takeaway
The SSD works because four kinds of hiding all landed together. Physics gave a cell that traps electrons behind a wall thin enough to tunnel through, good for 10 years. Lithography let manufacturers stack a billion of those cells into a fingernail-sized die. Wear-leveling spread the damage so no block died early. And in 2013 LDPC error correction finally caught up to the shrinking cells, correcting 40 flipped bits per kilobyte on chips too dirty for the old BCH math. That last piece is what made three-bit TLC flash commercial, turning storage that corrupts itself into storage you trust with your only copy. None of the earlier links mattered until the math caught the physics. The drive still lies to you every time you save: the cells are wearing, the bits are flipping, the raw chip is failing. You just never see the damage, because the correction runs faster than the progress bar.
References
- JSAC 2013 LDPC Flash (2013) tier1
Wang & Wolf, Enhanced Precision Through Multiple Reads for LDPC Decoding in Flash Memory, IEEE JSAC, 2013
- IEEE Milestone Floating Gate EEPROM 1976-1978 (1978) tier2
Milestones: The Floating Gate EEPROM, 1976-1978, IEEE History Center, 2013
- Micron NFTL guide (2011) tier2
Micron NAND Flash Translation Layer User Guide, 2011
- Recent Progress on 3D NAND Flash Technologies (2021) tier2
Park et al, Electronics, 2021: review of 3D NAND scaling, layer stacking and density trends
